The present invention relates to logic gates and, more particularly, to current mode or differential logic gates.
Current mode logic gates are well known in the art. In these types of gates a "tail" current is switched between differential circuit paths to provide complementary output signals in response to a particular coded logic input signals applied to the gate. Although prior art CML gates typically function at lower speeds, many, if not all, suffer problems in high speed circuit applications where matched output signal rise/fall times and input loading effects become critical.
For example, one common prior art CML gate uses a "multiplier" approach to steer the tail current to load resistors for various logic functions. In this approach, the two load resistors are connected to unequal numbers of transistor collectors, typically, for a three input gate, one load resistor may be connected to seven collectors while the other is connected to only one collector. Hence, the first output has more capacitance loading than the other such that the output switches at a slower rate than the latter in response to the logic input signal. This load to collector connection ratio varies for different logic gates (AND, OR, etc.) making propagation delays gate dependent. Further, another disadvantage of this type of gate is that the logic input signals are loaded by an unequal number of transistors which results in code dependency of the response delays. In a system where several signals are processed in a parallel fashion, unequal rise/fall time delays and their dependency on the logic function and the code causes undesirable timing differences between the different signals.
Hence, a need exist for a high speed CML gate in which the switched tail current paths are matched and in which the output capacitance loading is reduced and matched to provide matched rise/fall gate delays at the output of the gate thus making propagation delays both function and code independent.